Metadata-Version: 2.1
Name: hdl_registers
Version: 3.0.0
Summary: The hdl_registers project is an open-source HDL register generator fast enough to be run in
Home-page: https://hdl-registers.com
Author: Lukas Vik
Author-email: 2767848-LukasVik@users.noreply.gitlab.com
License: BSD 3-Clause License
Project-URL: Documentation, https://hdl-registers.com/
Project-URL: Changelog, https://hdl-registers.com/release_notes.html
Project-URL: Source, https://gitlab.com/hdl_registers/hdl_registers
Project-URL: Issues, https://gitlab.com/hdl_registers/hdl_registers/-/issues
Classifier: Development Status :: 5 - Production/Stable
Classifier: License :: OSI Approved :: BSD License
Classifier: Natural Language :: English
Classifier: Intended Audience :: Developers
Classifier: Operating System :: Microsoft :: Windows
Classifier: Operating System :: MacOS :: MacOS X
Classifier: Operating System :: POSIX :: Linux
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Requires-Python: >=3.6
Description-Content-Type: text/x-rst
Provides-Extra: dev

About hdl_registers
===================

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.. |pic_website| image:: https://hdl-registers.com/badges/website.svg
  :alt: Website
  :target: https://hdl-registers.com

.. |pic_gitlab| image:: https://hdl-registers.com/badges/gitlab.svg
  :alt: Gitlab
  :target: https://gitlab.com/hdl_registers/hdl_registers

.. |pic_gitter| image:: https://badges.gitter.im/owner/repo.png
  :alt: Gitter
  :target: https://gitter.im/tsfpga/tsfpga

.. |pic_pip_install| image:: https://hdl-registers.com/badges/pip_install.svg
  :alt: pypi
  :target: https://pypi.org/project/hdl-registers/

.. |pic_license| image:: https://hdl-registers.com/badges/license.svg
  :alt: License
  :target: https://hdl-registers.com/license_information.html

.. |pic_python_line_coverage| image:: https://hdl-registers.com/badges/python_coverage.svg
  :alt: Python line coverage
  :target: https://hdl-registers.com/python_coverage_html

The hdl_registers project is an open-source HDL register generator fast enough to be run in
real time.
It can easily be plugged into your development environment so that VHDL register code generation is
done before each build and simulation run.
For your FPGA release artifacts it can generate headers and documentation.

**See documentation on the website**: https://hdl-registers.com

**Check out the source code on gitlab**: https://gitlab.com/hdl_registers/hdl_registers

The typical use case is to let hdl_registers parse a ``.toml`` file with register definitions that
make up a register map.
It is also possible to work directly with the Python abstractions as well, without using a
data file.
The following code can be generated by the tool:

* VHDL package containing the register constant values, as well as a type with all the registers
  and their modes.
  This can be used with a
  `generic register file <https://hdl-modules.com/modules/reg_file/reg_file.html#axi-lite-reg-file-vhd>`_
  in your VHDL code.
* HTML website with documentation of the registers and constants.
* C header with constant values, register addresses, and register field information.
* C++ header and implementation with constant values, and setters/getters for
  registers and fields.
  The header has an abstract interface class which can be used for mocking.
