Metadata-Version: 2.1
Name: peakrdl-regblock
Version: 0.8.0
Summary: Compile SystemRDL into a SystemVerilog control/status register (CSR) block
Home-page: https://github.com/SystemRDL/PeakRDL-regblock
Author: Alex Mykyta
Author-email: amykyta3@github.com
Project-URL: Documentation, http://peakrdl-regblock.readthedocs.io
Project-URL: Source, https://github.com/SystemRDL/PeakRDL-regblock
Project-URL: Tracker, https://github.com/SystemRDL/PeakRDL-regblock/issues
Classifier: Development Status :: 3 - Alpha
Classifier: Programming Language :: Python
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3.6
Classifier: Programming Language :: Python :: 3.7
Classifier: Programming Language :: Python :: 3.8
Classifier: Programming Language :: Python :: 3.9
Classifier: Programming Language :: Python :: 3.10
Classifier: Programming Language :: Python :: 3 :: Only
Classifier: Intended Audience :: Developers
Classifier: License :: OSI Approved :: GNU General Public License v3 (GPLv3)
Classifier: Operating System :: OS Independent
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Requires-Python: >=3.6
Description-Content-Type: text/markdown
License-File: LICENSE

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# PeakRDL-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the [PeakRDL project](https://peakrdl.readthedocs.io).

## Documentation
See the [PeakRDL-regblock Documentation](http://peakrdl-regblock.readthedocs.io) for more details
